1. Field of the Invention
The present invention relates to a signal transmission technology, more particularly to a technology for a termination circuit for matching a plurality of segments of impedance of a transmission line.
2. Description of the Related Art
In a memory interface based on double data rate 2 (DDR2) rating stipulated by Joint Electron Device Engineering Council (JEDEC), it is required that a termination circuit should be provided on the controller side of memory.
It is required that the termination circuit on the controller side in a DDR2 interface is activated when a controller receives data, and it is inactivated when the controller transmits data. It is stipulated that the matched impedance of a transmission line should be 75 ohms. Therefore, if a controller and memory are connected 1 to 1, the termination resistance value is made to be 75 ohms. However, if a controller and memory are connected 1 to 2, the terminal resistance value can be switched to 150 ohms. Furthermore, the termination circuit is required to form Thevenin termination.
One configuration of a termination circuit for meeting such a requirement is shown in FIG. 1.
In FIG. 1, four resistors 101a, 101b, 101c and 101d are disposed in each data transmission line leading to memory 200 in a controller 100. The resistors 101a and 101c are connected in parallel between a transmission line and a power supply line, and the resistors 101b and 101d are connected in parallel between the transmission line and a ground line. The resistance value of each of the resistors 101a, 101b, 101c and 101d is 300 ohms. Therefore, this circuit forms Thevenin termination and its termination resistance value becomes 75 ohms.
In this case, if one resistor between the transmission line and the power supply line (for example, resistor 101c) and one resistor between the transmission line and the ground line (for example, resistor 101d) of the four resistors 101a, 101b, 101c and 101d is severed from the transmission line, its termination resistance value becomes 150 ohms while the Thevenin termination is maintained by the remaining ones (for example, resistors 101a and 101b). If the four resistors 101a, 101b, 101c and 101d are all further severed from the transmission line, the termination circuit is inactivated.
One detailed configuration of the termination circuit on the semiconductor substrate in a semiconductor device is shown in FIG. 2. In FIG. 2, P-channel type metal oxide semiconductor (MOS) transistors 111a and 11c provided between a transmission line 102 and a power supply line 103 correspond to the resistors 101a and 101c, respectively, and N-channel type MOS transistors 111b and 111d correspond to the resistors 101b and 101c, respectively.
P-channel type MOS transistors 111e and N-channel type MOS transistor 111f are used to connect/disconnect the P-channel type MOS transistor 111a and 111c and the N-channel type MOS transistors 111b and 111d to/from the transmission line 102, and are formed in such a way that the resistance value (so-called “on resistance”) between the drain terminal and the source terminal can be made sufficiently low when operating them in a saturation region.
The P-channel type MOS transistors (hereinafter called “P-type transistor”) 111a and 111c are switched on if the signal level of its gate terminal is L (low level), and the N-channel type MOS transistors (hereinafter called “N-type transistor”) 111b and 111d are switched on if the signal level of its gate terminal is H (high level). In this case, its gate width is formed in such a way that the on resistance of each of the P-type transistors 111a and 111c and the N-type transistors 111b and 111d can become 300 ohms. Therefore, if the respective signal levels of the gate terminals of these transistors 111a, 111b, 111c and 111d are all controlled so as to be switched on, this circuit forms Thevenin termination and its termination resistance value becomes 75 ohms.
In this case, if one of the P-type transistors 111a and 111c (for example, P-type transistor 111c) and one of the N-type transistors 111b and 111d (for example, N-type transistor 111d) are controlled so as to be switched off, its terminal resistance value becomes 150 ohms while the Thevenin termination are maintained by the remaining transistors (for example, P-type transistor 111a and N-type transistor 111b). Furthermore, if the signal level of each of the gate terminals of the P-type transistor 111e and the N-type transistor 111f is controlled so as to be switched off, the termination circuit is inactivated.
Since the termination circuit shown in FIG. 2 utilizes the respective on resistance of transistors 111a, 111b, 111c and 111d, the termination circuit has the following problems.    (1) If the gate threshold voltage of each of the P-type transistors 111a and 111c is expressed by VthP, the proportional relationship between voltage change ΔVDs and current change ΔIds between the drain terminal and the source terminal degrades when the potential of the transmission line 102 drops below the VthP, and the resistance value between the transmission line 102 and the power supply line 103 exceeds a target value.    (2) If the gate threshold voltage of each of the N-type transistors 111b and 111d, and voltage between the gate terminal and the source terminal at the time of on operation are expressed by VthN and Vgs (that is, potential VDD of the power supply line 103), respectively, the proportional relationship between voltage change ΔVDs and current change ΔIds caused between the drain terminal and the source terminal degrades when the potential of the transmission line 102 exceeds Vgs-VthN, and the resistance value between the transmission line 102 and the ground line 104 exceeds a target value.
Therefore, the terminal resistance value varies depending on a transmission signal if viewed from the transmission line 102 side, and the signal transmission quality of the transmission line 102 degrades.
For this problem, for example, Japanese Patent Application No. 2002-344300 discloses a technology for suppressing the dispersion of termination resistance values by enabling a transistor used to operate as a termination resistor in a non-saturation region and also controlling the gate terminal voltage of a transistor based on a reference resistance to obtain proper on resistance.
However, this technology requires an analog circuit for generating gate terminal voltage for proper on resistance in a transistor based on the reference resistance.
For example, in the termination circuit of a memory interface, a lot of transistors must be provided as resistors since there are a lot of transmission lines. However, it is often difficult in connection with other circuits to unify a plurality of wiring layouts to the gate terminal of each transistor. Therefore, in the technology disclosed in the Japanese Patent Application No. 2002-344300, voltage to be supplied to the gate terminal cannot be unified among transistors due to these different wiring layouts. As a result, the on operation resistance values cannot be unified, and the transmission line cannot always be sufficiently matched.